1. Field of the Invention
The present invention relates to low power autonomous peripheral circuits and methods. The novel low power autonomous peripheral circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
Shown in FIG. 1 is a typical general purpose computer system 10. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. In the Related Application, I have disclosed circuits adapted to operate in the sub-threshold domain.
Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 12 comprising: a central processing unit (“CPU”) 14; at least one random-access memory (“RAM”) facility 16; at least one Flash memory (“Flash”) facility 18; one or more timers (“Timers”) 20; at least one input/output master (“I/O Master”) facility 22; at least one input/output slave (“I/O Slave”) facility 24; at least one analog to digital converter (“ADC”) facility 26; a power management unit (“PMU”) 28; and a clock generator (“Clock Generator”) facility 30. A system bus (“System Bus”) 32 interconnects the several MCU facilities 14-30, and a clock distribution bus (“Clock Bus”) 34 distributes all clock signals developed by the Clock Generator 30 to the respective clocked facilities. As is known, development of the several clocks is generally controlled by information written to one or more control registers within Clock Generator 30 via the System Bus 32, and by system power state information typically provided by the PMU 28.
Traditional low power System On Chip (“SOC”) implementations supporting various peripherals such as analog signal-to-digital-conversion (“ADC”), Inter-Integrated Circuit (“I2C”) input/output (“I/O”) interfaces, or Serial Peripheral Interface (“SPI”) I/O interfaces utilize various methods for reducing the overall system power consumption. These approaches include a combination of software and hardware mechanisms for disabling the power hungry digital and analog circuitry and also control gating the clocking circuitry when the peripherals are not being used by the system. As an example, FIG. 3 illustrates, in block diagram form, one traditional circuit facility 34 for processing the data from an ADC conversion. As is illustrated, CPU/software 36 provides inputs for power control 38 and clock control 40. Power control 38 and power switch 42 provide power to ADC 46 as a function of inputs from CPU/software 36. The power provided to ADC 46 power may be gated on and off as a function of the inputs provided by CPU/software 36. Clock control 38 and clock enables 44 provide various clocks to ADC 46 as a function of inputs provided by CPU/software 36. The various clock provided by clock enables 44 may vary as a function of the inputs provided by CPU/software 36. ADC Controls 48 receives data from ADC 46 and interfaces with the CPU for the transfer of data to and from CPU/Software 36. As is known to one of ordinary skill in the art of computer peripheral design, CPU/software 36 may include software for analyzing, averaging or comparing the data. These traditional approaches incur a certain amount of overhead for managing power switches, clock enables, data collection, and similar operations, requiring the central processing unit (“CPU”) to remain active, thus consuming additional power.
What is needed is a method and apparatus adapted to support autonomous peripheral operations while consuming less power than known prior art.